Title :
A low-speed BIST framework for high-performance circuit testing
Author :
Speek, H. ; Kerkhoff, H.G. ; Shashaani, M. ; Sachdev, M.
Author_Institution :
MESA Res. Inst., Twente Univ., Enschede, Netherlands
Abstract :
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed
Keywords :
CMOS digital integrated circuits; VLSI; automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; CMOS; VLSI; clock frequencies; design-for-test methodology; high frequency capabilities; high-performance circuit testing; implementation aspects; logic testing; low-speed BIST framework; Built-in self-test; Circuit testing; Clocks; Costs; Design engineering; Fault detection; Frequency; Manufacturing; Timing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843865
