DocumentCode
2014835
Title
Hardware-in-the-loop simulation of PV systems in micro-grids using SysML models
Author
Gutierrez, A. ; Chamorro, H.R. ; Jimenez, J.F. ; Villa, L.F.L. ; Alonso, C.
Author_Institution
Universidad de los Andes, Department of Electrical and Electronic Engineering, Bogotá, Colombia
fYear
2015
fDate
12-15 July 2015
Firstpage
1
Lastpage
5
Abstract
This paper outlines a methodology for modeling photovoltaic systems in embedded hardware. This methodology uses the HiLeS platform to transform SysML models in Petri nets and generate VHDL code. The proposed methodology is intended for Hardware-in-the-Loop simulations of power converters and PV panels in microgrids. In addition, this methodology allows the design of MPPT controllers for their direct implementation in FPGA.
Keywords
Analytical models; Field programmable gate arrays; Load modeling; Mathematical model; Numerical models; Petri nets; Power electronics; Boost converter; FPGA; Hardware-in-the-Loop; MPPT; Petri net; Photovoltaic; SysML;
fLanguage
English
Publisher
ieee
Conference_Titel
Control and Modeling for Power Electronics (COMPEL), 2015 IEEE 16th Workshop on
Conference_Location
Vancouver, BC, Canada
Type
conf
DOI
10.1109/COMPEL.2015.7236466
Filename
7236466
Link To Document