Title :
Testability alternatives exploration through functional testing
Author :
Ferrandi, F. ; Ferrara, G. ; Fornara, G. ; Fummi, F. ; Sciuto, D.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
The aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different classes of architectures implementing the same specification. A unique test set is derived on the behavioral specification, based on a functional error model, which shows a high correlation with the single stuck-at-gate-level fault model. Such a test set is then tailored to the particular gate-level implementation by transforming it into a specific test sequence, based on the scheduling adopted by the high-level synthesis. Experimental results show that the application of such test sequences allows one to accurately evaluate the testability of the architecture in terms of gate-level fault coverage, in a fraction of the time required by a gate-level test pattern generator
Keywords :
automatic test pattern generation; fault diagnosis; high level synthesis; integrated circuit testing; logic testing; behavioral specification; functional error model; functional testing; gate-level fault coverage; gate-level implementation; high-level approach; high-level synthesis; single stuck-at-gate-level model; test pattern generation; test sequence; test set; testability analysis; Circuit faults; Circuit synthesis; Circuit testing; Delay; Design for testability; Information analysis; Pattern analysis; Performance analysis; Performance evaluation; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843874
