Title :
Design of an 8:1 MUX at 1.7 Gbit/s in 0.8 μm CMOS technology
Author :
Navarro, J. ; Noije, W. A M Van
Author_Institution :
Lab. de Sistemas Integrados, Sao Paulo Univ., Brazil
Abstract :
The design of an 8:1 multiplexer circuit, for SDH/SONET data transmission systems, is presented. In order to achieve maximum transmission rates, new circuits, high speed input/output converters for ECL-CMOS levels and modified true single phase clocked (TSPC) cells, as well as new techniques for clock buffer optimization, were applied. The multiplexer was implemented in a 0.8 μm CMOS process (0.7 μm effective length) achieved 1.7 Gbit/s rate and 42.6 μW/MHz power consumption at 5 V. These results were compared to a previous implementation (in the same process), and to other recently published works, showing superior performances
Keywords :
CMOS digital integrated circuits; SONET; circuit optimisation; clocks; data communication equipment; multiplexing equipment; synchronous digital hierarchy; 0.8 micron; 1.7 Gbit/s; 5 V; 8:1 multiplexer circuit; CMOS technology; SDH/SONET data transmission systems; clock buffer optimization; input/output converters; power consumption; transmission rates; true single phase clocked cells; CMOS process; CMOS technology; Circuits; Clocks; Data communication; Energy consumption; Flip-flops; Multiplexing; SONET; Synchronous digital hierarchy;
Conference_Titel :
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-8409-7
DOI :
10.1109/GLSV.1998.665207
