A Multi-DSP based Simulator for Architecture and High Density Algorithm Exploration

Author

Khan, FoziaNoor ; Khan, Shoab

Author_Institution

Center for Adv. Studies in Eng., Islamabad

fYear

2005

fDate

24-25 Dec. 2005

Firstpage

1

Lastpage

5

Abstract

This paper presents a novel architecture of a multi DSP based simulator. The simulator can be used for evaluating numerous DSP configurations in multi processor environment across several parameters and criteria. The simulator can also evaluate performance of different multi processor scheduling algorithms for high density signal processing applications. The simulator is designed to explore design space for up to OC48 media gateway controller running different VOIP algorithms

Keywords

Internet telephony; digital simulation; internetworking; processor scheduling; signal processing; OC48 media gateway controller; VOIP algorithms; high density algorithm exploration; high density signal processing applications; multi processor scheduling algorithms; multiDSP based simulator; Algorithm design and analysis; Codecs; Computer aided software engineering; Digital signal processing; Engines; Internet telephony; Processor scheduling; Scheduling algorithm; Signal processing algorithms; Streaming media; DSP; OC-48 Media gateway; Scheduler; Simulator; VOIP;

fLanguage

English

Publisher

ieee

Conference_Titel

9th International Multitopic Conference, IEEE INMIC 2005

Conference_Location

Karachi

Print_ISBN

0-7803-9429-1

Electronic_ISBN

0-7803-9430-5

Type

conf

DOI

10.1109/INMIC.2005.334392

Filename

4133407