Title :
Analysis of adaptive CMOS down conversion mixers
Author :
Sandalc, Can K. ; Kiaei, Sayfe
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Abstract :
Analysis of CMOS direct conversion architecture with adaptive DC offset compensation is presented. Due to process mismatches and local oscillator (LO) crosstalk, DC offsets up to 30 mV are observed at the mixer output. For a practical direct conversion or zero-IF down-conversion system, the incoming RF signal can be as low as -100 dBm or few microvolts at this stage and any LO coupling will cause a DC offset orders of magnitude larger than the received signal. The DC offset needs to be effectively reduced to prevent the consecutive gain stages from entering saturation and destroying the RF signal. To achieve this, an adaptive DC shifting circuit is presented. Adding a tunable DC offset on the LO signal can effectively counteract the output DC offset by exploiting the quadratic LO dependence of the process mismatch induced offsets. In addition to that, DSP approaches for adaptively generating the control signals for the DC shifting circuitry are investigated
Keywords :
CMOS analogue integrated circuits; adaptive signal processing; compensation; crosstalk; mixers (circuits); nonlinear network analysis; DSP approaches; LO crosstalk; adaptive CMOS down conversion mixers; adaptive DC offset compensation; adaptive DC shifting circuit; direct conversion architecture; process mismatch induced offsets; tunable DC offset; zero-IF receivers; Circuits; Computer architecture; Coupling circuits; Crosstalk; DC generators; Digital signal processing; Image converters; Linearity; Local oscillators; RF signals; Radio frequency; Signal generators; Signal processing; Transceivers; Tunable circuits and devices; Voltage;
Conference_Titel :
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-8409-7
DOI :
10.1109/GLSV.1998.665210