Design and Tradeoff Analysis of an Area Efficient Viterbi Decoder

Author

Saleem, Shahzad ; Khan, Shoab Ahmad

Author_Institution

Center for Adv. Studies in Eng., Islamabad

fYear

2005

fDate

24-25 Dec. 2005

Firstpage

1

Lastpage

5

Abstract

The Viterbi decoder is widely used in digital communication systems. It performs the maximum-likelihood decoding of convolutional codes received from a noisy channel Depending on the application (terrestrial, satellite, digital modems, digital cellular telephone applications and others) a Viterbi decoder must be designed to meet specific requirements such as small area, high speed or maximum efficiency. This paper presents a novel architecture for area efficient Viterbi decoder, which can be used for low bitrate applications. The design schedules all computations on less number of ACS processing elements as compared to parallel implementation assuming that a lot of clock cycles are available for decoding

Keywords

Viterbi decoding; adders; clocks; convolutional codes; digital communication; logic design; telecommunication channels; ACS processing elements; area efficient Viterbi decoder; clock cycles; convolutional codes; digital communication systems; low bitrate applications; noisy channel; tradeoff analysis; Bit rate; Computer architecture; Convolutional codes; Digital communication; Maximum likelihood decoding; Modems; Processor scheduling; Satellites; Telephony; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

9th International Multitopic Conference, IEEE INMIC 2005

Conference_Location

Karachi

Print_ISBN

0-7803-9429-1

Electronic_ISBN

0-7803-9430-5

Type

conf

DOI

10.1109/INMIC.2005.334400

Filename

4133415