A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS

Author

Ghahramani, Mohammad Mahdi ; Ferriss, Mark A. ; Flynn, Michael P.

Author_Institution

Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers -2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm².

Keywords

CMOS digital integrated circuits; Zigbee; digital phase locked loops; phase detectors; radio transmitters; radiofrequency integrated circuits; sigma-delta modulation; 1-bit quantizer; CMOS; IEEE802.15.4 standard; TDC-based digital PLL; digital ΣΔ fractional-N PLL; digital PLL-based transmitter; frequency 2.4 GHz; phase detector; power 17 mW; self-calibrated two-point modulation scheme; size 130 nm; voltage 1.2 V; Detectors; Frequency shift keying; Phase locked loops; Transmitters; Voltage-controlled oscillators; Delta-sigma; MSK; fractional-N; phase-locked loop; synthesizer;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5940590

Filename

5940590