Failure analysis and stress simulation in small multichip BGAs

This paper examines one of the common modes of structural failure in multichip BGAs, determines its locations within the package structure, relates it to the stresses generated in the reliability tests under which it occurs, and by Finite Element simulations, determines an explanation for the failure, and finally proposes a method to avoid this failure mechanism. Several designs of multichip BGA substrates were manufactured and production silicon assembled into them. These were all 14×22 mm 119 ball PBGA. These were subjected to a set of package reliability tests, until some units failed electrical test. The failed units were analysed and the physical location and shape of the failure was determined in many cases. From this information, the mechanical mode of failure for each unit was determined. In addition there was sufficient information in some of the analyses to provide definite suggestions as to the mechanism of failure. Meanwhile, Finite Element Analysis was performed using simplified representations of the multichip BGAs, in order to find the locations of highest stress, and the expected modes of failure. This data was matched to the failure modes found in the physical analysis. Some novel failure analysis techniques were used to expose the damage in the failed units. A particular failure mode occurred frequently in temperature cycle, and the sites of failure were located by failure analysis. The failure was due to open circuit in the copper tracks in the top layer of the substrate caused by cracking in the solder resist directly underneath the edge of the die attach fillet. Finite element analysis was carried out and the location of the actual failures was found to be a local zone of high tensile stress in the solder resist