DocumentCode :
2016124
Title :
A Technique for Using Model Checkers to Teach Formal Specifications
Author :
Salamah, Salamah ; Gates, Ann Q.
Author_Institution :
Dept. of Comput. & Software Eng., Embry-Riddle Aeronaut. Univ., Dayton, OH
fYear :
2008
fDate :
14-17 April 2008
Firstpage :
181
Lastpage :
188
Abstract :
The difficulty of writing, reading, and understanding formal specifications is one of the main obstacles in adopting formal verification techniques such as model checking and runtime verification. Introducing concepts in formal methods in an undergraduate program is essential for training a workforce that can develop and test high-assurance systems. This paper presents educational outcomes and outlines an instructive component that can be used in an undergraduate course to teach formal approaches and languages. The component uses a model checker and a specification tool to teach Linear Temporal Logic (LTL), a specification language that is widely used in a variety of verification tools. The paper also introduces a novel technique that analyzes LTL specifications by using the SPIN model checker to elucidate the behaviors accepted by the specifications.
Keywords :
computer aided instruction; educational courses; formal specification; formal verification; formal methods; formal specifications; formal verification; linear temporal logic; model checkers; runtime verification; undergraduate course; Computer science; Computer science education; Formal specifications; Formal verification; Logic; Runtime; Software engineering; Specification languages; System testing; Writing; Formal Specifications; LTL; Model Checking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software Engineering Education and Training, 2008. CSEET '08. IEEE 21st Conference on
Conference_Location :
Charleston, SC
ISSN :
1093-0175
Print_ISBN :
978-0-7695-3144-1
Type :
conf
DOI :
10.1109/CSEET.2008.25
Filename :
4556964
Link To Document :
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