• DocumentCode
    2016182
  • Title

    A highly-modular pipelined VLSI architecture for 2-D FIR digital filters

  • Author

    Hsieh, Cheng-Teh ; Kim, Seung P.

  • Author_Institution
    Dept. of Electr. Eng., Polytech. Univ., Brooklyn, NY, USA
  • Volume
    1
  • fYear
    1996
  • fDate
    18-21 Aug 1996
  • Firstpage
    137
  • Abstract
    A highly-modular pipelined VLSI architecture for two-dimensional (2-D) finite impulse response (FIR) digital filters is presented. This approach decomposes the 2-D discrete convolutions into pipelined summations of parallel 1-D discrete convolutions, so that modular structure is obtained. The advantages of this architecture are: (i) regular structure with high modularity, (ii) fully pipelined operation with maximum utilization of the hardware resources, (iii) the real-time processing ability with low system latency
  • Keywords
    FIR filters; VLSI; convolution; pipeline processing; real-time systems; two-dimensional digital filters; 2D FIR digital filters; discrete convolutions; hardware resources; modular pipelined VLSI architecture; pipelined summations; real-time processing ability; regular structure; system latency; Computer architecture; Delay; Digital filters; Finite impulse response filter; Hardware; Multiplexing; Real time systems; Throughput; Two dimensional displays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996., IEEE 39th Midwest symposium on
  • Conference_Location
    Ames, IA
  • Print_ISBN
    0-7803-3636-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1996.594060
  • Filename
    594060