ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests

Author

Meneghesso, G. ; Santirosi, S. ; Novarini, E. ; Contiero, C. ; Zanoni, E.

Author_Institution

Dipt. di Elettronica e Inf., Padova Univ., Italy

fYear

2000

fDate

2000

Firstpage

270

Lastpage

275

Abstract

In this paper we will present data concerning the ESD robustness of smart power protection structures (fabricated in Bipolar, CMOS, DMOS, BCD technology) for input-output circuits. A comparison between the robustness of “p-body” and “p-well” based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. Failure analysis has been carried out by means of SEM device cross-sections

Keywords

electrostatic discharge; failure analysis; integrated circuit testing; power integrated circuits; protection; scanning electron microscopy; ESD robustness; HBM test; SEM device cross-section; TLP test; failure analysis; input-output circuit; smart power protection structure; Biological system modeling; CMOS technology; Circuits; Electrostatic discharge; Leakage current; Protection; Robustness; Semiconductor device modeling; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2000. Proceedings. 38th Annual 2000 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

0-7803-5860-0

Type

conf

DOI

10.1109/RELPHY.2000.843926

Filename

843926