Title :
A 100GHz phase-locked loop in 0.13µm SiGe BiCMOS process
Author :
Kang, Shinwon ; Chien, Jun-Chau ; Niknejad, Ali M.
Author_Institution :
Berkeley Wireless Res. Center, Univ. of California at Berkeley, Berkeley, CA, USA
Abstract :
A fully integrated 100GHz phase-locked loop (PLL) is demonstrated in 0.13μm SiGe BiCMOS process. The PLL employs a fundamental-frequency differential Colpitts voltage-controlled oscillator (VCO) with 8.3% tuning range, which achieves a phase noise of -124.5dBc/Hz at 10MHz offset, and a single-ended output power of 3dBm. The FoM of this VCO is the best among 90-100GHz VCOs. A Miller divider, operating from 50GHz up to 130GHz, is designed and the Gilbert-mixer phase detector is used to attenuate reference spurs. The total lock range of the PLL is from 92.7 to 100.2GHz, the phase noise is -102dBc/Hz at 1MHz offset, and reference spurs are not observable. The PLL dissipates 570mW and occupies 1.21mm2.
Keywords :
BiCMOS integrated circuits; frequency dividers; mixers (circuits); phase detectors; phase locked loops; phase noise; voltage-controlled oscillators; BiCMOS process; Gilbert-mixer phase detector; Miller divider; PLL; VCO; frequency 10 MHz; frequency 100 GHz; frequency 50 GHz to 130 GHz; frequency 90 GHz to 100 GHz; frequency 92.7 GHz to 100.2 GHz; fully integrated phase-locked loop; fundamental-frequency differential Colpitts voltage-controlled oscillator; lock range; phase noise; power 570 mW; reference spurs; single-ended output power; size 0.13 mum; BiCMOS integrated circuits; Phase locked loops; Phase noise; Power generation; Silicon germanium; Solid state circuits; Voltage-controlled oscillators; 100GHz; Gilbert-mixer phase detector (PD); Miller divider; mm-wave applications; phase noise; phase-locked loop (PLL); voltage-controlled oscillator (VCO);
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-8293-1
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2011.5940606
