Analysis of the effects of time delay in clock recovery circuits based on phase-locked loops

Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain, are investigated by numerical simulations. Furthermore, simple expressions governing the stability properties of the loop, in the presence of time delay, are derived. For this purpose, three standard loop filters are considered: a Pl filter, a low pass (LP) filter and an active lag (AL) filter. The derived expressions are used to perform an optimisation in terms of the selected loop filters.