DocumentCode
2016645
Title
CORDIC: Novel sequential and Pipelined Architectures and Performance issues
Author
Ali, Usman ; Sheikh, Umair Ali
Author_Institution
COMSATS Inst. of Inf. Technol., Abbottabad
fYear
2005
fDate
24-25 Dec. 2005
Firstpage
1
Lastpage
6
Abstract
This paper presents a novel and simple sequential design of CORDIC for the calculation of Sine and Cosine of an angle. Design reduces the hardware requirement by using a single adder/subtractor module for all the iterations and for both Sine and Cosine calculation. Sequential design is implemented and synthesized in MAX plus 2 and time diagram is presented. A parallel extension is also discussed, which would increase the speed. Performance of the proposed design is compared with other general architectures available
Keywords
digital arithmetic; iterative methods; pipeline processing; CORDIC architecture; coordinate rotation digital computer; hardware requirement; pipeline architecture; sequential architecture; Computer architecture; Design automation; Field programmable gate arrays; Hardware; Information technology; Iterative algorithms; Navigation; Read only memory; Signal processing algorithms; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
9th International Multitopic Conference, IEEE INMIC 2005
Conference_Location
Karachi
Print_ISBN
0-7803-9429-1
Electronic_ISBN
0-7803-9430-5
Type
conf
DOI
10.1109/INMIC.2005.334423
Filename
4133438
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