Reliability assessment through defect based testing

In this paper it is shown that a small linear variation of poly critical dimensions, effective channel length, and transistor threshold voltage caused by non-controlled process variations will result in an exponential variation in the of state conductivity of a transistor. For the first time, it is shown, that the application of the percolation theory makes it possible to integrate the contribution of short channel MOSFET´s to the standby current of deep-sub-micron CMOS microprocessors taking into consideration the above process variations. It is proved that a Fault model, which consists of an equivalent effective MOSFET with inherent defects, can represent a CMOS VLSI circuit in standby mode. The model permits the use of standby current versus voltage test results for screening, built-in reliability and the process monitoring. The viability of this model is examined on 32-bit 0.25 μm CMOS microprocessors. Results obtained on the product line confirm the model and show a strong correlation between rejected devices and infant mortality failures