DocumentCode
2017344
Title
Modeling of shift register-based ATM switch
Author
Agarwal, Sandeep ; El Guibaly, F.
Author_Institution
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
fYear
1998
fDate
19-21 Feb 1998
Firstpage
146
Lastpage
151
Abstract
In this paper, we present the modeling of shift register-based ATM switch to find the cell loss probability, throughput and delay. The results are compared with other switch architectures based on input queueing, input smoothing, output queueing and completely shared buffering. It is observed that although our switch is an input-buffered switch, its performance is better than other switches based on traditional queuing approaches
Keywords
asynchronous transfer mode; delays; electronic switching systems; probability; queueing theory; shift registers; switching networks; cell loss probability; delay; input queueing; input smoothing; modeling; output queueing; shared buffering; shift register-based ATM switch; switch architecture; throughput; Asynchronous transfer mode; Computer architecture; Delay; Numerical simulation; Protocols; Scheduling; Shift registers; Smoothing methods; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location
Lafayette, LA
ISSN
1066-1395
Print_ISBN
0-8186-8409-7
Type
conf
DOI
10.1109/GLSV.1998.665216
Filename
665216
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