DocumentCode
2017384
Title
Single chip digital down converter architecture
Author
Petrowski, Mike ; Chester, David B. ; Young, W. Ronald
Author_Institution
Harris Semiconductor, Melbourne, FL, USA
Volume
1
fYear
1993
fDate
27-30 April 1993
Firstpage
349
Abstract
The architecture and algorithmic advancements of the Harris HSP50016 digital downconverter (DDC) are described. The DDC is a fully programmable single-chip downconverter designed to perform intermediate frequency (IF) to baseband processing for communications signal processing. The operation and specification of each major function within the DDC are described, and justification for key specifications is given. The end-to-end performance of the DDC is shown, and the methodology used for measuring the performance is explained.<>
Keywords
digital signal processing chips; frequency convertors; Harris HSP50016 digital downconverter; algorithmic advancements; architecture; communications signal processing; end-to-end performance; fully programmable single-chip downconverter; methodology; operation; specification;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on
Conference_Location
Minneapolis, MN, USA
ISSN
1520-6149
Print_ISBN
0-7803-7402-9
Type
conf
DOI
10.1109/ICASSP.1993.319127
Filename
319127
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