I/O bandwidth optimization of VLSI architectures for matrix product-like algorithms

The authors address the problem of input/output (I/O) bandwidth optimization of VLSI architectures implementing matrix-product-like algorithms, such as vector quantization or relational operations on databases. The high I/O bandwidth required by these applications can be decreased at the expense of on-chip memories. The purpose is, for a given application, to find the architectural parameters that, for a given I/O rate, minimize the on-chip memory size so as to keep the maximal part of chip area for computation. For this purpose, a general model of the architecture is proposed in which the on-chip memory size is expressed as a function of I/O rate, space-time allocation of computations onto the processing elements, vector dimension, and input and output data wordlengths. I/O optimization minimizes the memory size as a function of I/O bandwidth. I/O optimization is illustrated for the implementation of relational operations on databases.<>