DocumentCode :
2017491
Title :
Assembly process development of 2.5D integration for high performance processer
Author :
Liu, Haiyan ; Jiang, Feng ; Xue, Kai ; Yu, Daquan ; Liu, Xiaoyang
Author_Institution :
National Center for Advanced Packaging, Wuxi, China
fYear :
2015
fDate :
11-14 Aug. 2015
Firstpage :
161
Lastpage :
163
Abstract :
Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With the development of through-silicon via (TSV) technology, silicon-based device integrations have become the main stream of 3D packaging technologies. In this study, the assembly of high performance processor chip and TSV interposer is developed. From bottom to top assembly process was applied and the warpage of the interposer was effectively suppressed. Flying-Probe testing showed a good conducting of the package.
Keywords :
Annealing; Assembly; Packaging; Silicon; Substrates; 2.5D; assembly; underfill; warpage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2015 16th International Conference on
Conference_Location :
Changsha, China
Type :
conf
DOI :
10.1109/ICEPT.2015.7236566
Filename :
7236566
Link To Document :
بازگشت