DocumentCode
2017628
Title
An architecture of full-search block matching for minimum memory bandwidth requirement
Author
Tuan, Jen-Chien ; Jen, Chein-Wei
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
1998
fDate
19-21 Feb 1998
Firstpage
152
Lastpage
156
Abstract
In this paper an architecture of full-search block matching motion estimation suitable for high quality video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth will increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford. This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done by setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value, only a little overhead is introduced. Due to the reduction of memory bandwidth, the costs of the frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency is still achieved. Simple and regular interconnections are featured to ensure high speed operation by an efficient and distributed local memory organization
Keywords
VLSI; digital signal processing chips; image matching; motion estimation; parallel architectures; video signal processing; block matching motion estimation; distributed local memory organisation; frame memory bandwidth bottleneck; full-search block matching; high quality video; high speed operation; large frame size video; local memory size optimisation; maximum data reuse property; minimum memory bandwidth requirement; regular interconnections; Bandwidth; Computer architecture; Costs; Energy consumption; Hardware; Motion estimation; Random access memory; Scheduling; Systolic arrays; US Department of Transportation; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location
Lafayette, LA
ISSN
1066-1395
Print_ISBN
0-8186-8409-7
Type
conf
DOI
10.1109/GLSV.1998.665217
Filename
665217
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