Title :
Ensuring IC Reliability by Automated Design Checks
Author :
Chawda, P. ; Rajeswaran, M. ; Joy, Joshua ; Suresh, P.R.
Author_Institution :
Texas Instrum., Bangalore
Abstract :
This paper describes a schematic tool for verification of voltage levels of the signal and power nets to ensure the reliability of devices in the complex designs. The tool traces voltage levels of all nets/devices from the primary I/O pins of full chip and flags wrong voltage levels for power and signal nets in IC designs. The checker increases the efficiency of designers while creating/verifying the schematic.
Keywords :
circuit CAD; integrated circuit design; integrated circuit reliability; automated design checks; complex designs; integrated circuit reliability; power nets; schematic tool; signal nets; Analog integrated circuits; Design automation; Digital control; Electric breakdown; Instruments; MOSFETs; Process design; Signal design; Voltage control;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-1014-9
DOI :
10.1109/IPFA.2007.4378083
