Parallel morphological image processing with an opto-electronic VLSI array processor

A parallel morphological image processor (MIP) has been developed onto a full-custom optoelectronic VLSI design by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. The optical input/output (I/O) array processor performs morphological functions on the optodetected binary image with a programmable structuring element of any size. A language called MIPL is defined for parallel morphological image processing and fully supported by the MIP hardware. An 8*8 array processor prototype chip has been designed in 1.6-mm*1.6-mm silicon area using the MOSIS 2- mu m CMOS process.<>