Title :
A 550–1050MHz +30dBm class-E power amplifier in 65nm CMOS
Author :
Zhang, Ronghui ; Acar, Mustafa ; Van der Heijden, Mark P. ; Apostolidou, Melina ; De Vreede, Leo C N ; Leenaerts, Domine M W
Author_Institution :
Delft Univ. of Technol., Delft, Netherlands
Abstract :
A 65nm CMOS broadband two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To reduce the peak drain-source voltage and improve reliable operation, sub-optimum class-E operation is applied. The PA is followed by a broadband output matching network implemented as an off-chip two-stage LC ladder. The measurements with a 5.0V supply voltage for the power stage and 2.4V for the driver stage show a drain efficiency >; 67% and a power-added efficiency (PAE) >; 52% with a Pout >; 30dBm within 550MHz-1050MHz. The output power variation is within 1.0dB and efficiency variation is less than 13%. The highest efficiency is observed at 700MHz with peak drain efficiency of 77% and peak PAE of 65% at a Pout of 31dBm and 17dB power gain. By using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off from 30dBm.
Keywords :
CMOS analogue integrated circuits; driver circuits; power amplifiers; CMOS; broadband output matching network; class-E power amplifier; driver stage; dynamic supply modulation; frequency 550 MHz to 1050 MHz; high voltage extended-drain device; off-chip two-stage LC ladder; peak drain-source voltage reduction; power-added efficiency; size 65 nm; voltage 2.4 V; voltage 5 V; Broadband communication; CMOS integrated circuits; CMOS technology; Impedance; Impedance matching; Power generation; Switches; Broadband; CMOS power amplifier; class-E;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-8293-1
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2011.5940653
