Title :
A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation
Author :
Callender, Steven ; Niknejad, Ali M.
Author_Institution :
Berkeley Wireless Res. Center, Univ. of California at Berkeley, Berkeley, CA, USA
Abstract :
This paper presents the design of a 1 GHz Delay-Locked Loop (DLL) with embedded phase interpolation. The DLL was designed in a 0.13μm SiGe BiCMOS process and provides a measured single-tap phase range of 50ps (18°) with an average and worst-case phase resolution of 1.36ps (0.49°) and 5ps (1.8°), respectively. This translates to beamsteering resolutions of <; 3.5mm in free space when integrated into mm-wave imagers that utilize time-domain beamforming. The DLL has an average output rms-jitter (across all interpolation steps) of 860fs. The DLL consumes 33 mW of power and occupies an area of 0.185mm2.
Keywords :
BiCMOS integrated circuits; delay lock loops; integrated circuit design; radar imaging; BiCMOS process; beamsteering resolutions; embedded phase interpolation; measured single-tap phase; phase-adjustable delay-locked loop; time-domain beamforming; Clocks; Delay; Image resolution; Imaging; Interpolation; Phase measurement; Transceivers; BiCMOS integrated circuits; Delay locked loop; phase interpolation; radar imaging;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-8293-1
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2011.5940657
