Title :
Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test
Author :
Cheng-Cheng Yen ; Ming-Dou Ker
Author_Institution :
Nat.Chiao-Tung Univ., Hsinchu
Abstract :
The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mum CMOS technology.
Keywords :
CMOS integrated circuits; integrated circuit testing; thyristors; time-domain analysis; transients; CMOS integrated circuit; electrical fast transient test; silicon-controlled rectifier test structure; size 0.18 mum; time domain; transient-induced latchup; Anodes; CMOS integrated circuits; CMOS technology; Cathodes; Circuit testing; Electromagnetic compatibility; Integrated circuit testing; Microelectronics; Thyristors; Voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-1014-9
DOI :
10.1109/IPFA.2007.4378095
