A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver

Author

Goel, Ankush ; Analui, Behnam ; Hashemi, Hossein

Author_Institution

Univ. of Southern California, Los Angeles, CA, USA

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

A monolithic 100Hz-6GHz reconfigurable Vector Signal Analyzer (VSA) and Software Defined Receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wide-band interference scenarios, is presented. The 130nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or harmonics. A monolithic VSA/SDR enables various commercial and military wireless solutions.

Keywords

CMOS integrated circuits; microwave integrated circuits; radio receivers; software radio; CMOS chip; commercial wireless solutions; frequency 100 Hz to 6 GHz; military wireless solutions; monolithic reconfigurable vector signal analyzer; size 130 nm; software defined receiver; two-step up-down conversion heterodyne scheme; wideband interference scenarios; Baseband; CMOS integrated circuits; Radio frequency; Receivers; Semiconductor device measurement; Wideband; Wireless communication; CMOS; RADIO FREQUENCY; RECEIVER WIDEBAND;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5940676

Filename

5940676