DocumentCode
2018805
Title
Fault tolerant Block Based Neural Networks
Author
Haridass, Sai Sri Krishna ; Hoe, David H K
Author_Institution
Electr. Eng. Dept., Univ. of Texas at Tyler Tyler, Tyler, TX, USA
fYear
2010
fDate
7-9 March 2010
Firstpage
357
Lastpage
361
Abstract
Block Based Neural Networks (BBNNs) have shown to be a practical means for implementing evolvable hardware on reconfigurable fabrics for solving a variety of problems that take advantage of the massive parallelism offered by a neural network approach. This paper proposes a method for obtaining a fault tolerant implementation of BBNNs by using a biologically inspired layered design. At the lowest level, each block has its own online detection and correcting logic combined with sufficient spare components to ensure recovery from permanent and transient errors. Another layer of hierarchy combines the blocks into clusters, where a redundant column of blocks can be used to replace blocks that cannot be repaired at the lowest level. The hierarchical approach is well-suited to a divide-and-conquer approach to genetic programming whereby complex problems are subdivided into smaller parts. The overall approach can be implemented on a reconfigurable fabric.
Keywords
fault tolerant computing; genetic algorithms; neural nets; reconfigurable architectures; correcting logic; divide-and-conquer approach; evolvable hardware; fault tolerant block based neural networks; genetic programming; massive parallelism; online detection; reconfigurable fabrics; transient errors; Circuit faults; Fabrics; Fault detection; Fault tolerance; Fault tolerant systems; Integrated circuit interconnections; Logic; Network topology; Neural network hardware; Neural networks; Block based network; Fault detection and correction; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory (SSST), 2010 42nd Southeastern Symposium on
Conference_Location
Tyler, TX
ISSN
0094-2898
Print_ISBN
978-1-4244-5690-1
Type
conf
DOI
10.1109/SSST.2010.5442804
Filename
5442804
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