Late Hardware/Software Partitioning by Using SystemC Functional Models

In this paper a partly unified hardware/software design flow is presented. It uses System C as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design language for hardware and software design, system simulations at different abstraction levels are simplified. In combination with the concept of high level synthesis, this design flow reduces the effort after the partitioning and thus also significantly reduces the extra effort of a possible re partitioning between hardware and software. As proof of concept the receiver components of a VoIP engine have been implemented. The data flow dominant RTP protocol has been realized on an FPGA and the results of different hardware/software partitionings are presented.