Title :
A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS
Author :
Elsayed, Mohamed ; Abdul-Latif, Mohammed ; Sánchez-Sinencio, Edgar
Author_Institution :
Analog & Mixed Signal Center, Texas A&M Univ., College Station, TX, USA
Abstract :
An architectural solution for designing a low-reference-spur PLL is presented. A spur frequency-booster block is inserted between the phase-frequency-detector and the charge pump to boost the charge pump´s input frequency. Hence, the reference-spurs theoretically vanish. The proposed technique adds additional degrees of freedom in the design of PLLs to reduce the spur level without sacrificing neither the loop bandwidth nor the voltage-controlled oscillator´s gain. A prototype is fabricated using UMC 90 nm digital CMOS technology and achieves -74 dBc reference-spur suppression along with (KVCO/fref) ratio of 17 at a (fBW/fref) ratio of 1/20.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; voltage-controlled oscillators; digital CMOS; loop bandwidth; low reference spur PLL; phase frequency detector; size 90 nm; spur frequency booster block; spur frequency boosting PLL; spur rejection; voltage controlled oscillator gain; Bandwidth; CMOS integrated circuits; CMOS technology; Charge pumps; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; Phase locked loop (PLL); low spur; spur-frequency boosting;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-8293-1
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2011.5940706
