The design of residue number system arithmetic units for a VLSI adaptive equalizer

Author

Lee, Inseop ; Jenkins, W. Kenneth

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

19-21 Feb 1998

Firstpage

179

Lastpage

184

Abstract

This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper

Keywords

VLSI; adaptive equalisers; adders; application specific integrated circuits; least mean squares methods; multiplying circuits; residue number systems; ASIC; LMS algorithm; RNS architecture; VLSI adaptive equalizer; adder; all-digital adaptive equalizer; arithmetic units; binary-to-residue converter; filter; high level hardware simulation tool; multiplier; residue number system; residue-to-binary converter; update algorithm; Adaptive algorithm; Adaptive equalizers; Adaptive filters; Algorithm design and analysis; Application specific integrated circuits; Arithmetic; Dynamic range; Equations; Hardware; Least squares approximation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665222

Filename

665222