Enhancing random access scan for soft error tolerance

Recent work on random access scan (RAS) has shown its advantages in reducing test application time, test data volume and test power over those of the conventional serial scan (SS). This paper is first to examine the soft error tolerance of RAS. The RAS structure not only improves error tolerance ability during test, it also provides capability to efficiently enhance the circuits error tolerance during normal function mode. A single event upset (SEU) induced error in a flip-flop of SS propagates to other flip-flops via scan while the error for RAS remains localized to the affected flip-flop. We enhance the error tolerance by applying the built-in soft error resilience (BISER) and triple modular redundancy (TMR) techniques to RAS and serial scan (SS). Results show that the BISER implementation for RAS can save on average 20.51% hardware over BISER applied to SS. TMR-RAS saves on average 179.28% over TMR-SS for ISCAS89 benchmarks.