DocumentCode
2019336
Title
Investigation of properties of 36-bit adders for creation of DSP blocks on FPGA
Author
Bystritskaya, Natalia A. ; Smolyannikov, Ilia A. ; Kurganskii, Sergey I.
Author_Institution
Voronezh State Univ., Voronezh, Russia
fYear
2010
fDate
June 30 2010-July 4 2010
Firstpage
143
Lastpage
146
Abstract
In this paper 36-bit ripple-carry, carry-skip, carry-select and carry-lookahead adders intended for using in field programmable gate arrays are investigated. These schemes implemented in CMOS 0.18 μm technology are compared for their performance. The size of adders is estimated.
Keywords
adders; digital signal processing chips; field programmable gate arrays; 36-bit adders; CMOS; DSP blocks; FPGA; carry lookahead adders; field programmable gate arrays; Digital signal processing; Seminars; Ripple-carry adder; carry-lookahead adder; carry-select adder; carry-skip adder;
fLanguage
English
Publisher
ieee
Conference_Titel
Micro/Nanotechnologies and Electron Devices (EDM), 2010 International Conference and Seminar on
Conference_Location
Novosibirsk
Print_ISBN
978-1-4244-6626-9
Type
conf
DOI
10.1109/EDM.2010.5568844
Filename
5568844
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