DocumentCode :
2019714
Title :
The Chinese Abacus method: can we use it for digital arithmetic?
Author :
Maloberti, Franco ; Gang, Chen
Author_Institution :
Integrated Microsyst. Lab., Pavia Univ., Italy
fYear :
1998
fDate :
19-21 Feb 1998
Firstpage :
192
Lastpage :
195
Abstract :
This paper discusses how to apply the approach used in the Chinese Abacus to implement digital arithmetic. Firstly, we examine the representations and the basic techniques used in the Chinese Abacus; then, we propose an MOS realization of the basic functions required; finally, we discuss a novel 12 bit full adder based on the Chinese Abacus method. Simulations of 0.5 μm CMOS realizations showed that a parallel solution can run at 200 MHz while a pipeline realization can achieve 1 GHz of clock frequency. The complexity of the circuit is quite limited; thus, the use of the Chinese Abacus approach results in a competitive technique with respect to conventional methodologies
Keywords :
MOS logic circuits; adders; digital arithmetic; parallel processing; pipeline arithmetic; 0.5 micron; 1 GHz; 12 bit; 200 MHz; Chinese Abacus method; MOS realization; digital arithmetic; full adder; parallel solution; pipeline realization; Adders; CMOS technology; Calculators; Circuit simulation; Clocks; Digital arithmetic; Electronic circuits; Frequency; Helium; Pipelines;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location :
Lafayette, LA
ISSN :
1066-1395
Print_ISBN :
0-8186-8409-7
Type :
conf
DOI :
10.1109/GLSV.1998.665224
Filename :
665224
Link To Document :
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