The interfacial thermo-mechanical reliability of 3D memory-chip stacking with through silicon via array

Thermal stress in through silicon vias (TSVs) caused by the mismatch of coefficient of thermal expansion (CTE) between the filling material and silicon is a key challenge for three-dimensional electronic packaging due to the sophisticated inner structures. In most of the previous studies, the thermomechanical properties of TSV structured chips were analyzed in a unit cell so as to simplify the problem. In this simulation study, a seven-layered memory-chip stacking model is constructed, and finite element method is used to evaluate the influence of the inner structure on thermo-mechanical stresses and the interfacial reliability of the TSV structure package. The simulation results show that, due to the large CTE and low yield strength of copper compared to silicon, the stress concentrated zone locates at the chip and PCB interface on the copper side. The placement of TSVs is one of the main considerations in IC design because it has a significant influence on the thermal stress. Use of Pb-free solder such as SAC305 has almost no influence on the maximum stress in TSV interconnects. The radius of keep-away-zone, where transistors should not be arranged, is two times of that of TSVs. TSV parameters have some influence on the interfacial stress. The maximum interfacial stress increases with decreasing diameters of TSVs when the diameter ratio of TSV to Cu nail (i.e., DTSV/DCu) keeps unchanged.