Fast Processing Multiplier

This paper presenting the alternative binary arithmetic multiplier which constructed by implementing the shift/copy process to serve the partial product generation line with two levels carry lookahead adders (CLAs) to perform the final operands adding in order to speed up the carry propagation along the array. The design is particular structured for 4-bits and 8-bits multiplier for testing purposes. It is then analysis together with the conventional bit array multiplier topology and the comparison has been presented in term of functionality, speed efficiency and area consumption. Both synthesis and simulation of the multipliers are performed in Altera Quartus II, by using fully synthesizable hardware description language in VHDL without any design constraints