Discrete event model verification using system morphism

Author

Hong, Ki Jung ; Kim, Tag Gon

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

5

fYear

2001

fDate

2001

Firstpage

3057

Abstract

Model verification is to check the correctness of an implemented simulation program against a model specification. The paper proposed an automatic model verification methodology based on the I/O function level system morphism. The verification methodology establishes a mapping between all possible I/O event sequences of specification and those of implementation. The DEVS formalism is used as a specification language; implementation is assumed to be done by any simulation language or general purpose languages. Realization of the proposed methodology is presented with an example of verification for an assembly process model

Keywords

computational complexity; discrete event simulation; discrete event systems; formal verification; DEVS formalism; I/O event sequences; I/O function level system morphism; assembly process model; automatic model verification methodology; discrete event model verification; implemented simulation program; mapping; model specification; system morphism; Computational modeling; Computer science; Computer simulation; Discrete event simulation; Mathematical model; Object oriented modeling; Software testing; Specification languages; System testing; Technical Activities Guide -TAG;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Man, and Cybernetics, 2001 IEEE International Conference on

Conference_Location

Tucson, AZ

ISSN

1062-922X

Print_ISBN

0-7803-7087-2

Type

conf

DOI

10.1109/ICSMC.2001.971985

Filename

971985