Discrete event model verification using system morphism

Model verification is to check the correctness of an implemented simulation program against a model specification. The paper proposed an automatic model verification methodology based on the I/O function level system morphism. The verification methodology establishes a mapping between all possible I/O event sequences of specification and those of implementation. The DEVS formalism is used as a specification language; implementation is assumed to be done by any simulation language or general purpose languages. Realization of the proposed methodology is presented with an example of verification for an assembly process model