Investigation of thermal-mechanical stress and chip-packaging-interaction issues in low-k chips

The structural integrity on the low-k layers is a major reliability concern on three dimensional packaging technology. Because low-k materials used in dies have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied thermal mechanical stress due to packaging. The stress problem due to differences in dimension and material properties of various materials in the package in a large temperature range has caused a serious impact on reliability and yield of electronic components; hence the thermal stress problem has become an obstacle to the further development of packaging. This paper takes a product for the CPI assessment and creates an equivalent model to do simulation. A model consists of 4 sub-model is used to study the effect of CPI on a 10 layers interconnect structure in this work. Packaging of a 40nm technology node chip has been chosen in this study. Then different parameters such as polyimide opening, bumping diameter and bumping height are evaluated to show the effect on low-k material. The results showed that the stress in low-k materials mainly is caused by the local CTE mismatch between Cu interconnects and dielectric material.