Measuring STI Stress Effect on CMOS Transistor by Stepping through the Channel Width

This paper proposed a method that can measure the shallow trench isolation (STI) stress effect on transistor in the direction of channel width. Instead of implanting the entire channel (fixed width of 10mum), one portion of the channel (with fixed implant opening width of 0.5mum) was only implanted. By using this method, the channel edge can be brought away from the STI edge, where the active area is under high compressive stress. The results show that when the effective channel is near to the STI edge (high transverse compressive stress), both NMOS and PMOS transistors have higher threshold voltage, Vt and lower drain current, Id