Optimization for solder layer thermal characteristics of the power transistor based on structure function

Nowadays, the solder layer failure between chip and metal frame is the most common failure mode of the power transistor. Accordingly, the optimization for solder layer thermal characteristics attracts more attention. In this paper, the optimization for solder layer thermal characteristics of the power transistor using a combined measurement and simulation approach is presented, and the approach is based on structure function. The transient temperature response of the tested package is measured by electrical method and structure function can be derived from transient temperature response. Then, a 3D numerical model consistent with the actual sample is established employing thermal CFD simulators. And different materials, thicknesses and areas of the solder layer of the model are simulated. Some valuable results are given in the simulation. Following conclusions can be drawn from these results: there is a non-linear relationship between the thermal conductivity of materials and the thermal resistance of solder layer, the thickness of the solder layer keeps a positive correlation with the thermal resistance and if the solder floor area is larger than the chip area, the additional area has no significant effect on the thermal resistance of the device. Compared with traditional methods, the test-simulation combined optimization is more effective and economic.