The Impact of Multiple-Gated Layout on the Drain-Source Current of pseudomorphic-HEMTS

The measurement and analysis to search the impact of multiple-gated structure of a GaAs based p-HEMT device towards the drain-source current (Ids) is presented here. The experimental works had been carried out on the GaAs wafer that consists of 2times60, 4times75 and 6times150 p-HEMT device layouts for the I-V characteristic. The I-V measurement was performed using on-wafer probing technique which applied semi-auto probe station and Keithley parameter analyzer to extract I-V curve. From the I-V data, it was found that the p-HEMT layout that had higher number of gates exhibited a significant impact on the Ids at the same Vgs bias value. The Ids of six-gated layout was improved about 40% as compared to 4-gated layout and about 60% to 2-gated layout. The effect on the I-V performance due to the number of gates in the layout has also been discussed in detail for circuit design applications