Current-mode differential logic circuits for low power digital systems

A current-mode differential logic scheme is introduced. By biasing in the subthreshold regime, the transistors are operated with maximum normalized transconductance, g_m/I. The rapid saturation of devices operated in subthreshold allows for radical scaling of supply voltages to only 300 mV. Application of a back-bias further increases the g_m/I of the transistors, and hence the gain of the gates. The back bias also assists in the reduction of stray junction and gate-bulk capacitance. Operating with small voltage swings, delays of a few hundred nanoseconds can be achieved with bias currents of 50 nA. This results in operational speeds of a few megahertz at greatly reduced power consumption compared to standard CMOS digital logic. Experimental results are presented and extrapolated to a scaled version of the circuit