Title :
Design of 8-bit SAR-ADC CMOS
Author :
Hassan, Hesham Ahmed ; Halin, Izhal Abdul ; Bin Aris, Ishak ; Bin Hassan, Mohd Khair
Author_Institution :
Fac. of Electr. & Electron. Eng., Univ. Putra Malaysia, Serdang, Malaysia
Abstract :
Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18¿m CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs.
Keywords :
CMOS integrated circuits; VLSI; analogue-digital conversion; integrated circuit design; logic circuits; sample and hold circuits; system-on-chip; SAR-ADC CMOS; SOC; analog-to-digital converter; control logic circuit; current-mode approach; low-power low-cost VLSI; sample-and-hold dummy switch compensation; signal to noise ratio distortion; size 0.18 mum; successive approximation register; system-on-chip circuit designs; voltage 1.8 V; word length 8 bit; Analog-digital conversion; CMOS technology; Digital-analog conversion; Logic arrays; Logic circuits; Low voltage; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Analog-to-digital converter; CMOS; comparator; digital-to-analog converter; low voltage; sample-and-hold;
Conference_Titel :
Research and Development (SCOReD), 2009 IEEE Student Conference on
Conference_Location :
UPM Serdang
Print_ISBN :
978-1-4244-5186-9
Electronic_ISBN :
978-1-4244-5187-6
DOI :
10.1109/SCORED.2009.5443038
