DocumentCode :
2022167
Title :
On implementation of fast, bit-serial loops
Author :
Vesterbacka, Mark ; Palmkvist, K. ; Wanhammar, Lars
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume :
1
fYear :
1996
fDate :
18-21 Aug 1996
Firstpage :
190
Abstract :
In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier
Keywords :
CMOS logic circuits; digital arithmetic; logic design; multiplying circuits; recursive filters; canonic signed-digit coding; coefficient encoding; digital filters; fast bit-serial loops; first-order recursive filter; latency models; processing elements; recursive algorithm; serial multiplication; serial/parallel multiplier; throughput; Adders; Circuits; Clocks; Computational modeling; Delay; Filters; Flip-flops; Pipeline processing; Quantization; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
Type :
conf
DOI :
10.1109/MWSCAS.1996.594083
Filename :
594083
Link To Document :
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