Opening the hole of the backside silicon and forming the alloy bump for TSVs

Cu revealing and back bump forming is critical in developing TSV technique. A novel process to reveal Cu and form back bump is described in this paper. The designed test wafer is temporary bonded and supported to a glass wafer, and thinned by grinding and polishing processes. To prevent metal migration, a BCB insulating layer is formed on the backside of the test wafer. The wafer is patterned and electroplated to form Cu bump, followed by Sn chemical plating. After the backside bump is formed, multilayer chip can be stacked together though TSV by Cu-Sn eutectic bonding. X-ray and SEM inspection are used to check the bonding quality of this 3D stacking process.