The development of 3D aerospace SRAM integration technology using silicon interposer

The new 3D SRAM integration technology using silicon interposer is proposed. To build this 3D SRAM integration, the design of 3D SRAM architecture is studied. And the electrical simulation of this design scheme is carried out. The maximum crosstalk noise is less than 10% of the power supply voltage. The access speed of 3D SRAM is increased from 37.7ns (sole circuit) to 41.6ns; Under the condition of high temperature and low pressure SS CASE, the output high-voltage is 2.42V, and output low-voltage is 0.56V. 3D SRAM sample is developed successfully using through-silicon via (TSV) technology. This verification sample consists of four conventional SRAM, then the four conventional SRAM are bonded on silicon interposer with chip-to-chip bonding. The shear stress of bumps on the SRAM is 21gf. The new 3D SRAM capacity increase four times than sole SRAM without changing the key design of SRAM.