DocumentCode
2023271
Title
High-Speed Memory-Efficient Network Intrusion Detection System
Author
Lin, Wei ; Wang, Xiaofei ; Qi, Yaxuan ; Pao, Derek ; Liu, Bin
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear
2009
fDate
19-25 April 2009
Firstpage
1
Lastpage
2
Abstract
In this paper, two-stage NIDS architecture is proposed, which aims to both increase the throughput and reduce memory cost. The contributions of this work are listed below.
Keywords
computer networks; security of data; NIDS architecture; high-speed memory-efficient network intrusion detection system; memory cost reduction; Computer science; Computer security; Doped fiber amplifiers; Impedance matching; Information technology; Inspection; Intrusion detection; Pattern matching; Throughput; White spaces;
fLanguage
English
Publisher
ieee
Conference_Titel
INFOCOM Workshops 2009, IEEE
Conference_Location
Rio de Janeiro
Print_ISBN
978-1-4244-3968-3
Type
conf
DOI
10.1109/INFCOMW.2009.5072152
Filename
5072152
Link To Document