DocumentCode
2023367
Title
System-level simulation of a noisy phase-locked loop
Author
Herzel, Frank ; Piz, Maxim
Author_Institution
IHP, Frankfurt, Germany
fYear
2005
fDate
3-4 Oct. 2005
Firstpage
193
Lastpage
196
Abstract
This paper presents a compact model of a noisy phase-locked loop (PLL) for inclusion in a time-domain system simulation. The phase noise of the reference is modeled as a Wiener process, and the phase noise contribution of the voltage-controlled oscillator (VCO) is described as an Ornstein-Uhlenbeck process. The model is applied to phase error modeling for a 60 GHz OFDM system including correction of the common phase error. A close agreement is observed between the time-domain simulation and a frequency-domain model.
Keywords
OFDM modulation; phase locked loops; phase noise; stochastic processes; time-domain analysis; voltage-controlled oscillators; 60 GHz; OFDM system; Ornstein-Uhlenbeck process; PLL; VCO; Wiener process; common phase error; frequency-domain model; noisy phase-locked loop; phase noise; system-level simulation; voltage-controlled oscillator; Circuit simulation; Clocks; Error correction; Jitter; Low pass filters; OFDM; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005. European
Conference_Location
Paris
Print_ISBN
88-902012-0-7
Type
conf
Filename
1637183
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