A high purity 60 GHz-band single chip /spl times/8 multiplier with low phase noise

A single chip multiplier by eight (/spl times/8) MMIC for 52-62 GHz output frequency is presented. The multiplier consists of quadrupler stage followed by a high pass filter, an inter-stage amplifier and a doubler stage. The required output power is achieved by a two stage buffer amplifier on the output. An output power exceeding 7 dBm is achieved from 52 to 61 GHz. The rejection of the unwanted harmonics is better than 28 dB and the detected degradation of phase noise due to the circuit is less than 1 dB at 100 kHz offset from the carrier, compared to a theoretical value of 18.06 dB for a multiplier by eight. The bias configuration is optimized to reduce the number of the required bias voltages to three. The total power dissipation is 450 mW. The MMIC is designed and manufactured in a commercial 0.15 /spl mu/m PHEMT process from WIN foundry. To our knowledge this is the first reported MMIC multiplier by eight based on PHEMT technology.