Experimental validation of the power blurring method

Accurate estimation of temperature profiles from the underlying power dissipation profiles has become an important tool for chip designers and reliability engineers due to increasing power dissipation in ICs and associated thermal effects. IC´s surface temperature is conventionally calculated by finite element or finite difference solvers. These methods yield accurate results but the computation time could be several hours to obtain accurate dynamic temperature profiles with high spatial resolution. Previously, we have developed an ultra fast IC temperature profile calculation technique, named as Power Blurring (PB), which dramatically reduces the computation time by a factor of more than a thousand and keeps the error within 5% comparing to finite element analysis done by ANSYS. In this paper, the power blurring method is validated against experimental measurements using a thermal test chip which was designed based on 5-stage ring oscillators. The simulation results and the measurement data show good agreements.